In semi-conductor memory components a distinction is made between so-called function memory components (i.e. PLAs, PALs, etc.), and so-called table memory components, i.e. ROM components (ROM=Read Only Memory), and RAM components (RAM=Random Access Memory and/or read-write memory).
A RAM component is a memory device in which data is stored under a specified address, from which the data can later be read out again.
The corresponding address can be input into the RAM component by means of so-called address connections and/or address input pins; several, for instance 16, so-called data connections and/or data input/output pins (I/Os and/or Input/Outputs) are provided for storing and reading out data. By applying an appropriate signal (for instance a read/write signal) to a read/write selector connection and/or pin, a decision can (instantly) be made whether data is to be stored or read out.
Because a RAM component needs to be provided with as many storage cells as possible, it becomes important for the creation of these cells to be kept as simple as possible. With so-called SRAMs (SRAM=Static Random Access Memory) the individual memory cells for instance consist of a few, e.g. six, transistors and so-called DRAMs (DRAM=Dynamic Random Access Memory) usually of only a single suitably controlled capacitor, with the capacitance of which one bit at a time can be stored in the form of charge. This charge only persists for a short period, which means that a so-called “refresh” must be performed regularly, e.g. ca. every 64 ms.
In memory components, especially DRAM components, the individual memory cells—lying next to each other in a multitude of adjacent rows and columns—are arranged in a rectangular matrix (equally divided into several cell fields) and/or a rectangular array (equally divided into several cell fields).
In order to achieve a correspondingly high total storage capacity and/or to achieve the highest data read and/or write speed—instead of one single array—several, for instance four—essentially rectangular—individual arrays (so-called “memory banks”) can be arranged in a single RAM component and/or chip (“multi-bank chip”).
In order to perform a writing or reading operation, a specific, predetermined sequence of commands must be issued:
First for instance a corresponding word line—specifically allocated to a particular array—(and defined by the “row address”) is activated with the help of a word line activation command (activate command (ACT)) (for instance thereby that a corresponding master word line (MWL)—allocated to several superimposed cell fields and running through them is activated first, for instance by means of a master word line driver, for instance installed in a corresponding segment control area, and in reaction hereto the corresponding local word line (LWL), running through a corresponding singular cell filed is activated—for instance by a corresponding, local word line driver lying between the corresponding cell fields in a corresponding segment driver and/or sub-decoder area).
This causes the data values stored in the memory cells allocated to the corresponding word line to be read out by the sense amplifier allocated to that word line (“activated state” of the word line).
Then—with the help of a corresponding read or write (RD and/or WT) command—the appropriate data, accurately specified by the corresponding column address, is output by the sense amplifier(s) allocated to the bit line specified by the corresponding column address (or—conversely—data is then read into the corresponding memory cells).
Next the corresponding word line is deactivated again—with the help of a word line deactivation command (for instance a precharge (PRE) command)—and the corresponding array is prepared for the next word line activation command (activate command (ACT)).
The above sense amplifier(s) is/are in each case allocated to a sense amplifier area—lying between two cell fields—whereby—for reasons of space—one and the same sense amplifier can be allocated to two different cell fields (namely to the two cell fields directly adjacent to the corresponding sense amplifier area)—so-called “shared sense amplifier”.
Depending on whether data is to be read from the cell field to the left or to the right of the sense amplifier in question (or from the cell field lying above or below the sense amplifier in question), the corresponding sense amplifier is switched by means of appropriate switches to the corresponding cell field (in particular to the corresponding bit line allocated to the cell field in question) and/or electrically connected to the corresponding cell field, in particular to the corresponding bit line allocated to the cell field in question, or disconnected from the corresponding cell field (and/or the bit line allocated to the cell field in question) and/or electrically separated from the corresponding cell field (and/or from the bit line allocated to that corresponding cell field).
In semi-conductor components, more particularly memory components such as the above RAM, in particular DRAMs, an internal voltage level VINT used inside the component can differ from an externally used voltage level (supply voltage level) VDD used outside the component, for instance an external voltage supply made available to the semi-conductor component.
In particular, the internally used voltage level VINT can for instance be smaller than the externally used voltage level VDD—for instance the internally used voltage level VINT can amount to 1,5 V and the supply voltage level VDD for instance to between 1,5 V and 2,5 V.
In contrast to this, the above sub-decoder, in particular the above local word line driver devices, can be operated by means of “boosted” voltage levels, provided by one or several corresponding voltage booster devices (for instance by a voltage level VPP—for instance signifying a “high logic” word line signal—which is higher than the level VDD of the above external voltage, and by a voltage level VLL—representing a “low logic” word line signal for instance—which may for instance be smaller than 0 V).
The voltage booster device in question may for instance be installed in a central outside area (for instance in a boundary area of the semi-conductor component between two corresponding arrays) of the semi-conductor component, from where—by means of appropriate lines—the voltage levels VPP, VLL made available by the voltage booster devices can then be relayed to the corresponding sub-decoder and/or local word line driver.
This arrangement for instance has the disadvantage, that in particular when the sub-decoder and/or local word line drivers are placed relatively far away from the voltage booster devices—a relatively high voltage drop takes place.